1. Field of the Invention
The invention is related to the field of data communication, and in particular, to a data communication circuit that uses header detection signaling bits to align parallel data channels.
2. Statement of the Problem
Data communication systems transfer user data from one point to another. The user data is often transferred in packets that have headers. The headers carry address information that is used to identify and route the packets. The packets are transferred over channels that are arranged in parallel to provide simultaneous transmission of multiple packets. It is important to synchronize the parallel channels to a common clock so the system receiving the parallel channels can effectively detect and multiplex the user data.
One solution for synchronizing parallel channels uses circuitry to detect and align no the headers in the packets. The alignment of the headers also aligns the parallel channels. Unfortunately, the circuitry periodically mis-interprets the user data as a header and mistakenly aligns this mis-interpreted user data with the headers in the other parallel channels. Thus, the circuitry that is supposed to align the parallel channels actually mis-aligns the channels. Channel mis-alignment prevents the effective detection and multiplexing of the user data. The problem is further illustrated below with respect to FIG. 1.
The invention solves the problem with a data communication circuit that has improved channel alignment and clocking. The data communication circuit generates signaling bits that indicate headers to the alignment buffer. The alignment uses the signaling bits to align the parallel channels instead of having to detect the headers. As a result, the alignment buffer is prevented from detecting false headers in the user data and mis-aligning the parallel channels.
The data communication circuit includes a decoder and an alignment buffer. The decoder receives and decodes parallel (N) bit channels into parallel (M+X) bit channels where the variables N, M, and X are integers. The (M+X) bit channels include signaling bits that indicate headers in the parallel (M+X) bit channels. The decoder transfers the parallel (M+X) bit channels to the alignment buffer. The alignment buffer recovers and aligns parallel (M) bit channels using the signaling bits. The alignment buffer also generates a clock selection signal using the signaling bits. The alignment buffer transfers the aligned parallel (M) bit channels and the clock selection signal. The alignment buffer can have a length that is a multiple of a frame length for the (M) bit parallel channels.